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r8c/11 group single-chip 16-bit cmos microcomputer rej03b0034-0140z rev.1.40 sep 30, 2004 rev.1.40 sep 30, 2004 page 1 of 26 rej03b0034-0140z 1. overview this mcu is built using the high-performance silicon gate cmos process using a r8c/tiny series cpu core and is packaged in a 32-pin plastic molded lqfp. this mcu operates using sophisticated instructions featuring a high level of instruction efficiency. with 1m bytes of address space, it is capable of executing instructions at high speed. 1.1 applications electric household appliance, office equipment, housing equipment (sensor, security), general industrial equipment, audio, etc.
rev.1.40 sep 30, 2004 page 2 of 26 rej03b0034-0140z r8c/11 group 1. overview table 1.1 performance outline 1.2 performance outline table 1.1. lists the performance outline of this mcu. item performance cpu number of basic instructions 89 instructions shortest instruction execution time 50 ns (f(x in ) = 20 mh z , v cc = 3.0 to 5.5 v) 100 ns (f(x in ) = 10 mh z , v cc = 2.7 to 5.5 v) operating mode single-chip address space 1m bytes memory capacity see table 1.2. peripheral interrupt internal: 11 factors, external: 5 factors, function software: 4 factors, priority level: 7 levels watchdog timer 15 bits x 1 (with prescaler) timer timer x: 8 bits x 1 channel, timer y: 8 bits x 1 channel, timer z: 8 bits x 1 channel (each timer equipped with 8-bit prescaler) timer c: 16 bits x 1 channel circuits of input capture and output compare. serial interface ? channel clock synchronous, uart ? channel uart a/d converter 10-bit a/d converter: 1 circuit, 12 channels clock generation circuit 2 circuits ?ain clock generation circuit (equipped with a built-in feedback resistor) ?n-chip oscillator (high speed, low speed) on high-speed on-chip oscillator the frequency adjust- ment function is usable. oscillation stop detection function stop detection of main clock oscillation voltage detection circuit included power on reset circuit included port input/output: 22 (including led drive port), input: 2 (led drive i/o port: 8) electrical power supply voltage v cc = 3.0 to 5.5 v (f(x in ) = 20 mh z ) characteristics v cc = 2.7 to 5.5 v (f(x in ) = 10 mh z ) power consumption typ. 9 ma (v cc = 5.0 v, (f(x in ) = 20 mh z , high-speed mode) typ. 5 ma (v cc = 3.0 v, (f(x in ) = 10 mh z , high-speed mode) typ. 35 a (v cc = 3.0 v, wait mode, peripheral clock stops) typ. 0.7 a (v cc = 3.0 v, stop mode) flash memory program/erase voltage v cc = 2.7 to 5.5 v number of program/erase 100 times operating ambient temperature -20 to 85 ? -40 to 85 ? (d-version) package 32-pin plastic mold lqfp
rev.1.40 sep 30, 2004 page 3 of 26 rej03b0034-0140z r8c/11 group 1. overview 1.3 block diagram figure 1.1 shows this mcu block diagram. figure 1.1 block diagram timer x (8 bits) timer y (8 bits) timer z (8 bits) timer c (16 bits) watchdog timer (15 bits) memory rom (note 1) r 8 c s e r i e s c p u c o r e i / o p o r t p o r t p 0 8 p o r t p 1 8 port p3 5 multiplier s y s t e m c l o c k g e n e r a t o r x in -x out high-speed on-chip oscillator low-speed on-chip oscillator u a r t ( 8 b i t s ? 1 c h a n n e l ) p o r t p 4 1 2 pe r i p h e r a l f u n c t i o n s u a r t o r c l o c k s y n c h r o n o u s s e r i a l i / o ( 8 b i t s ? 1 c h a n n e l ) a / d c o n v e r t e r ( 1 0 b i t s ? 1 2 c h a n n e l s ) ram (note 2) n o t e 1 : r o m s i z e d e p e n d s o n m c u t y p e . n o t e 2 : r a m s i z e d e p e n d s o n m c u t y p e . r0l r0h r1h r1l r2 r3 a0 a1 fb s b isp usp intb pc f l g t i m e r
rev.1.40 sep 30, 2004 page 4 of 26 rej03b0034-0140z r8c/11 group 1. overview 1.4 product list table 1.2 lists the products. table 1.2 product list ram capacity rom capacity package type remarks type no. as of sep. 2004 flash memory version r5f21112fp 32p6u-a 8k bytes 512 bytes 32p6u-a 12k bytes 768 bytes 32p6u-a 16k bytes 1k bytes r5f21113fp r5f21114fp r5f21112dfp 32p6u-a 8k bytes 512 bytes 32p6u-a 12k bytes 768 bytes 32p6u-a 16k bytes 1k bytes r5f21113dfp r5f21114dfp d version figure 1.2 type no., memory size, and package package type: fp : 32p6u rom capacity: 2 : 8 kbytes. 3 : 12 kbytes. 4 : 16 kbytes. memory type: f: flash memory version type no. r 5 f 21 11 4 d fp r8c/11 group r8c/tiny series shows characteristics and others. d: operating ambient temperature 40 c to 85 c no symbol: operating ambient temperature 20 c to 85 c renesas mcu renesas semiconductors
rev.1.40 sep 30, 2004 page 5 of 26 rej03b0034-0140z r8c/11 group 1. overview package: 32p6u-a figure 1.3 pin configuration (top view) pin configuration (top view) 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 3 2 3 1 3 0 r 8 c / 1 1 g r o u p x i n / p 4 6 x o u t / p 4 7 (n o t e 1 ) v s s r e s e t v c c c n v s s p 1 7 / i n t 1 / c n t r 0 p 1 6 / c l k 0 p 1 5 / r x d 0 p 1 4 / t x d 0 p 3 7 / t x d 1 0 / r x d 1 p 3 0 / c n t r 0 / c m p 1 0 p 3 3 / i n t 3 / p 3 1 / t z o u t / c m p 1 1 p 3 2 / i n t 2 / c n t r 1 / c m p 1 2 i v c c 3 a v s s a v c c / v r e f p 0 3 / a n 4 p0 2 /an 5 p 0 1 / a n 6 p 0 0 / a n 7 /t x d 1 1 p 0 6 / a n 1 p 0 5 / a n 2 p 0 4 / a n 3 p 4 5 / i n t 0 p 1 0 / k i 0 / a n 8 / c m p 0 0 p1 1 /ki 1 /an 9 /cmp0 1 p1 2 /ki 2 /an 10 /cmp0 2 p1 3 /ki 3 /an 11 p 0 7 / a n 0 mode t c i n notes: 1. p4 7 functions only as an input port. 2. when using on-chip debugger, do not use pins p0 0 /an 7 /txd 11 and p3 7 /txd 10 /rxd 1 . 3. do not connect ivcc to vcc. 1.5 pin configuration figure 1.3 shows the pin configuration (top view).
rev.1.40 sep 30, 2004 page 6 of 26 rej03b0034-0140z r8c/11 group 1. overview signal name pin name i/o type power supply vcc, i input vss ivcc ivcc o analog power avcc, avss i supply input reset input ___________ reset i cnvss cnvss i mode mode i main clock input x in i main clock output x out o _____ int interrupt input _______ _______ int 0 to int 3 i key input interrupt _____ _____ ki 0 to ki 3 i timer x cntr 0 i/o ____________ cntr 0 o timer y cntr 1 i/o timer z tz out o timer c tc in i cmp0 0 to cmp0 3 , o cmp1 0 to cmp1 3 serial interface clk 0 i/o rxd 0 , rxd 1 i txd 0 , txd 10 ,o txd 11 reference voltage v ref i input a/d converter an 0 to an 11 i i/o port p0 0 to p0 7 , i/o p1 0 to p1 7 , p3 0 to p3 3 , p3 7 , p4 5 input port p4 6 , p4 7 i function apply 2.7 v to 5.5 v to the vcc pin. apply 0 v to the vss pin. this pin is to stabilize internal power supply. connect this pin to vss via a capacitor (0.1 f). do not connect to vcc. these are power supply input pins for a/d converter. connect the avss pin to vss. connect a capacitor between pins avcc and avss. l on this input resets the mcu. connect this pin to vss via a resistor. connect this pin to vcc via a resistor. these pins are provided for the main clock generat- ing circuit i/o. connect a ceramic resonator or a crys- tal oscillator between the x in and x out pins. to use an externally derived clock, input it to the x in pin and leave the x out pin open. ______ these are int interrupt input pins. these are key input interrupt pins. this is the timer x i/o pin. this is the timer x output pin. this is the timer y i/o pin. this is the timer z output pin. this is the timer c input pin. these are the timer c output pins. this is a transfer clock i/o pin. these are serial data input pins. these are serial data output pins. this is a reference voltage input pin for a/d con- verter. these are analog input pins for a/d converter. these are 8-bit cmos i/o ports. each port has an input/output select direction register, allowing each pin in that port to be directed for input or output indi- vidually. any port set to input can select whether to use a pull- up resistor or not by program. p1 0 to p1 7 also function as led drive ports. these are input only pins. 1.6 pin description table 1.3 shows the pin description table 1.3 pin description
rev.1.40 sep 30, 2004 page 7 of 26 rej03b0034-0140z r8c/11 group 2. central processing unit (cpu) 2. central processing unit (cpu) figure 2.1 shows the cpu registers. the cpu has 13 registers. of these, r0, r1, r2, r3, a0, a1 and fb comprise a register bank. there are two register banks. 2.1 data registers (r0, r1, r2 and r3) the r0 register consists of 16 bits, and is used mainly for transfers and arithmetic/logic operations. r1 to r3 are the same as r0. the r0 register can be separated between high (r0h) and low (r0l) for use as two 8-bit data registers. r1h and r1l are the same as r0h and r0l. conversely, r2 and r0 can be combined for use as a 32- bit data register (r2r0). r3r1 is the same as r2r0. data registers (note 1) address registers (note 1) frame base registers (note 1) program counter interrupt table register user stack pointer interrupt stack pointer static base register flag register note 1: these re g isters com p rise a re g ister bank. there are two re g ister banks. r0h(r0's high bits) b15 b8 b7 b0 r3 intbh usp isp sb aa aa aa aa aa aa aa aa aaaaaa aaaaaa aa aa a a aa aa aa aa aa aa c d z s b o i u ipl r0l(r0's low bits) r1h(r1's high bits) r1l(r1's low bits) r2 b31 r3 r2 a1 a0 fb b19 intbl b15 b0 pc b19 b0 b15 b0 flg b15 b0 b15 b0 b7 b8 reserved area carry flag debug flag zero flag sign flag register bank select flag overflow flag interrupt enable flag stack pointer select flag reserved area processor interrupt priority level the upper 4 bits of intb are intbh and the lower 16 bits of intb are intbl. figure 2.1. central processing unit register
rev.1.40 sep 30, 2004 page 8 of 26 rej03b0034-0140z r8c/11 group 2. central processing unit (cpu) 2.2 address registers (a0 and a1) the register a0 consists of 16 bits, and is used for address register indirect addressing and address register relative addressing. they also are used for transfers and logic/logic operations. a1 is the same as a0. in some instructions, registers a1 and a0 can be combined for use as a 32-bit address register (a1a0). 2.3 frame base register (fb) fb is configured with 16 bits, and is used for fb relative addressing. 2.4 interrupt table register (intb) intb is configured with 20 bits, indicating the start address of an interrupt vector table. 2.5 program counter (pc) pc is configured with 20 bits, indicating the address of an instruction to be executed. 2.6 user stack pointer (usp) and interrupt stack pointer (isp) stack pointer (sp) comes in two types: usp and isp, each configured with 16 bits. your desired type of stack pointer (usp or isp) can be selected by the u flag of flg. 2.7 static base register (sb) sb is configured with 16 bits, and is used for sb relative addressing. 2.8 flag register (flg) flg consists of 11 bits, indicating the cpu status. 2.8.1 carry flag (c flag) this flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit. 2.8.2 debug flag (d flag) the d flag is used exclusively for debugging purpose. during normal use, it must be set to ?? 2.8.3 zero flag (z flag) this flag is set to ??when an arithmetic operation resulted in 0; otherwise, it is ?? 2.8.4 sign flag (s flag) this flag is set to ??when an arithmetic operation resulted in a negative value; otherwise, it is ?? 2.8.5 register bank select flag (b flag) register bank 0 is selected when this flag is ??; register bank 1 is selected when this flag is ?? 2.8.6 overflow flag (o flag) this flag is set to ??when the operation resulted in an overflow; otherwise, it is ?? 2.8.7 interrupt enable flag (i flag) this flag enables a maskable interrupt. maskable interrupts are disabled when the i flag is ?? and are enabled when the i flag is ?? the i flag is cleared to ??when the interrupt request is accepted. 2.8.8 stack pointer select flag (u flag) isp is selected when the u flag is ?? usp is selected when the u flag is ?? the u flag is cleared to ??when a hardware interrupt request is accepted or an int instruction for software interrupt nos. 0 to 31 is executed. 2.8.9 processor interrupt priority level (ipl) ipl is configured with three bits, for specification of up to eight processor interrupt priority levels from level 0 to level 7. if a requested interrupt has priority greater than ipl, the interrupt is enabled. 2.8.10 reserved area when write to this bit, write "0". when read, its content is indeterminate.
rev.1.40 sep 30, 2004 page 9 of 26 rej03b0034-0140z r8c/11 group 3. memory 3. memory figure 3.1 is a memory map of this mcu. the address space extends the 1m bytes from address 00000 16 to fffff 16 . the internal rom is allocated in a lower address direction beginning with address 0ffff 16 . for example, a 16-kbyte internal rom is allocated to the addresses from 0c000 16 to 0ffff 16 . the fixed interrupt vector table is allocated to the addresses from 0ffdc 16 to 0ffff 16 . therefore, store the start address of each interrupt routine here. the internal ram is allocated in an upper address direction beginning with address 00400 16 . for example, a 1-kbyte internal ram is allocated to the addresses from 00400 16 to 007ff 16 . in addition to storing data, the internal ram also stores the stack used when calling subroutines and when interrupts are generated. special function registers (sfr) are allocated to the addresses from 00000 16 to 002ff 16 . peripheral func- tion control registers are located here. of the sfr, any space which has no functions allocated is reserved for future use and cannot be used by users. figure 3.1 memory map 00000 16 0yyyy 16 0ffff 16 002ff 16 00400 16 internal rom sfr (see chapter 4 for details.) 0ffdc 16 0ffff 16 undefined instruction overflow brk instruction address match single step watchdog timer,oscillation stop detection,voltage detection reset (reserved) type name 0xxxx 16 internal ram fffff 16 address 0xxxx 16 005ff 16 internal ram size 007ff 16 512 bytes 1k bytes 006ff 16 768 bytes address 0yyyy 16 0e000 16 internal rom size 0c000 16 8k bytes 16k bytes 0d000 16 12k bytes expanding area (reserved) r5f21114fp, r5f21114dfp r5f21113fp, r5f21113dfp r5f21112fp, r5f21112dfp notes : 1. blank spaces are reserved. no access is allowed.
rev.1.40 sep 30, 2004 page 10 of 26 rej03b0034-0140z r8c/11 group 4. special function register (sfr) w a t c h d o g t i m e r s t a r t r e g i s t e rw d t sx x 1 6 w a t c h d o g t i m e r c o n t r o l r e g i s t e rw d c0 0 0 x x x x x 2 p r o c e s s o r m o d e r e g i s t e r 0p m 00 0 1 6 s y s t e m c l o c k c o n t r o l r e g i s t e r 0c m 00 1 1 0 1 0 0 0 2 s y s t e m c l o c k c o n t r o l r e g i s t e r 1c m 10 0 1 0 0 0 0 0 2 a d d r e s s m a t c h i n t e r r u p t e n a b l e r e g i s t e ra i e rx x x x x x 0 0 2 p r o t e c t r e g i s t e rp r c r0 0 x x x 0 0 0 2 p r o c e s s o r m o d e r e g i s t e r 1p m 10 0 1 6 o s c i l l a t i o n s t o p d e t e c t i o n r e g i s t e ro c d0 0 0 0 0 1 0 0 2 i n t 0 i n p u t f i l t e r s e l e c t r e g i s t e ri n t 0 fx x x x x 0 0 0 2 0000 16 0001 16 0002 16 0003 16 0004 16 0005 16 0006 16 0007 16 0008 16 0009 16 000a 16 000b 16 000c 16 000d 16 000e 16 000f 16 0010 16 0011 16 0012 16 0013 16 0014 16 0015 16 0016 16 0017 16 0018 16 0019 16 001a 16 001b 16 001c 16 001d 16 001e 16 001f 16 0020 16 0021 16 0022 16 0023 16 0024 16 0025 16 0026 16 0027 16 0028 16 0029 16 002a 16 002b 16 002c 16 002d 16 002e 16 002f 16 0030 16 0031 16 0032 16 0033 16 0034 16 0035 16 0036 16 0037 16 0038 16 0039 16 003a 16 003b 16 003c 16 003d 16 003e 16 003f 16 a d d r e s s r e g i s t e rs y m b o l after reset a d d r e s s m a t c h i n t e r r u p t r e g i s t e r 0r m a d 00 0 1 6 0 0 1 6 x 0 1 6 a d d r e s s m a t c h i n t e r r u p t r e g i s t e r 1r m a d 10 0 1 6 0 0 1 6 x 0 1 6 w a t c h d o g t i m e r r e s e t r e g i s t e rw d t rx x 1 6 high-speed on-chip control register 0 hr0 00 16 h i g h - s p e e d o n - c h i p c o n t r o l r e g i s t e r 1h r 14 0 1 6 voltage detection register 1 vcr1 00 16 v o l t a g e d e t e c t i o n r e g i s t e r 2v c r 2x x x 0 0 0 0 0 1 6 v o l t a g e d e t e c t i o n i n t e r r u p t r e g i s t e rd 4 i n t0 0 1 6 1 2 2 2 01000001 2 3 4 x : u n d e f i n e d n o t e s : 1 . b l a n k c o l u m n s a r e a l l r e s e r v e d s p a c e . n o a c c e s s i s a l l o w e d . 2 . s o f t w a r e r e s e t o r t h e w a t c h d o g t i m e r r e s e t d o e s n o t a f f e c t t h i s r e g i s t e r . 3 . o w i n g t o r e s e t i n p u t . 4 . i n t h e c a s e o f r e s e t p i n = h r e t a i n i n g . 4. special function register (sfr) sfr(special function register) is the control register of peripheral functions. tables 4.1 to 4.4 list the sfr information table 4.1 sfr information(1) (1)
rev.1.40 sep 30, 2004 page 11 of 26 rej03b0034-0140z r8c/11 group 4. special function register (sfr) uart0 transmit interrupt control register s0tic xxxxx000 2 uart0 receive interrupt control register s0ric xxxxx000 2 uart1 transmit interrupt control register s1tic xxxxx000 2 uart1 receive interrupt control register s1ric xxxxx000 2 key input interrupt control register kupic xxxxx000 2 a/d conversion interrupt control register adic xxxxx000 2 int1 interrupt control register int1ic xxxxx000 2 int2 interrupt control register int2ic xxxxx000 2 int0 interrupt control register int0ic xx00x000 2 int3 interrupt control register int3ic xxxxx000 2 0040 16 0041 16 0042 16 0043 16 0044 16 0045 16 0046 16 0047 16 0048 16 0049 16 004a 16 004b 16 004c 16 004d 16 004e 16 004f 16 0050 16 0051 16 0052 16 0053 16 0054 16 0055 16 0056 16 0057 16 0058 16 0059 16 005a 16 005b 16 005c 16 005d 16 005e 16 005f 16 0060 16 0061 16 0062 16 0063 16 0064 16 0065 16 0066 16 0067 16 0068 16 0069 16 006a 16 006b 16 006c 16 006d 16 006e 16 006f 16 0070 16 0071 16 0072 16 0073 16 0074 16 0075 16 0076 16 0077 16 0078 16 0079 16 007a 16 007b 16 007c 16 007d 16 007e 16 007f 16 address register symbol after reset timer x interrupt control register txic xxxxx000 2 timer y interrupt control register tyic xxxxx000 2 timer z interrupt control register tzic xxxxx000 2 timer c interrupt control register tcic xxxxx000 2 compare 1 interrupt control register cmp1ic xxxxx000 2 compare 0 interrupt control register cmp0ic xxxxx000 2 x : undefined notes : 1. blank columns are all reserved space. no access is allowed. table 4.2 sfr information(2) (1)
rev.1.40 sep 30, 2004 page 12 of 26 rej03b0034-0140z r8c/11 group 4. special function register (sfr) 0080 16 0081 16 0082 16 0083 16 0084 16 0085 16 0086 16 0087 16 0088 16 0089 16 008a 16 008b 16 008c 16 008d 16 008e 16 008f 16 0090 16 0091 16 0092 16 0093 16 0094 16 0095 16 0096 16 0097 16 0098 16 0099 16 009a 16 009b 16 009c 16 009d 16 009e 16 009f 16 00a0 16 00a1 16 00a2 16 00a3 16 00a4 16 00a5 16 00a6 16 00a7 16 00a8 16 00a9 16 00aa 16 00ab 16 00ac 16 00ad 16 00ae 16 00af 16 00b0 16 00b1 16 00b2 16 00b3 16 00b4 16 00b5 16 00b6 16 00b7 16 00b8 16 00b9 16 00ba 16 00bb 16 00bc 16 00bd 16 00be 16 00bf 16 timer x register tx ff 16 timer y secondary tysc ff 16 external input enable register inten 00 16 prescaler y prey ff 16 uart0 transmit/receive mode register u0mr 00 16 uart0 transmit buffer register u0tb xx 16 xx 16 uart0 receive buffer register u0rb xx 16 xx 16 uart1 transmit/receive mode register u1mr 00 16 uart1 transmit buffer register u1tb xx 16 xx 16 uart1 receive buffer register u1rb xx 16 xx 16 uart0 bit rate register u0brg xx 16 uart0 transmit/receive control register 0 u0c0 00001000 2 uart0 transmit/receive control register 1 u0c1 00000010 2 uart1 bit rate register u1brg xx 16 uart1 transmit/receive control register 0 u1c0 00001000 2 uart1 transmit/receive control register 1 u1c1 00000010 2 uart transmit/receive control register 2 ucon 00 16 address register symbol after reset timer y, z mode register tyzmr 00 16 timer y primary typr ff 16 timer y, z waveform output control register pum 00 16 prescaler z prez ff 16 timer z secondary tzsc ff 16 timer y, z output control register tyzoc 00 16 timer x mode register txmr 00 16 prescaler x prex ff 16 timer count source setting register tcss 00 16 timer c register tc 00 16 00 16 key input enable register kien 00 16 timer c control register 0 tcc0 00 16 timer c control register 1 tcc1 00 16 capture, compare 0 register tm0 ff 16 ff 16 compare 1 register tm1 ff 16 ff 16 x : undefined notes : 1. blank columns are all reserved space. no access is allowed. timer z primary tzpr ff 16 table 4.3 sfr information(3) (1)
rev.1.40 sep 30, 2004 page 13 of 26 rej03b0034-0140z r8c/11 group 4. special function register (sfr) 00c0 16 00c1 16 00c2 16 00c3 16 00c4 16 00c5 16 00c6 16 00c7 16 00c8 16 00c9 16 00ca 16 00cb 16 00cc 16 00cd 16 00ce 16 00cf 16 00d0 16 00d1 16 00d2 16 00d3 16 00d4 16 00d5 16 00d6 16 00d7 16 00d8 16 00d9 16 00da 16 00db 16 00dc 16 00dd 16 00de 16 00df 16 00e0 16 00e1 16 00e2 16 00e3 16 00e4 16 00e5 16 00e6 16 00e7 16 00e8 16 00e9 16 00ea 16 00eb 16 00ec 16 00ed 16 00ee 16 00ef 16 00f0 16 00f1 16 00f2 16 00f3 16 00f4 16 00f5 16 00f6 16 00f7 16 00f8 16 00f9 16 03fa 16 00fb 16 00fc 16 00fd 16 00fe 16 00ff 16 01b3 16 01b4 16 01b5 16 01b6 16 01b7 16 a/d register ad xx 16 xx 16 a/d control register 0 adcon0 00000xxx 2 a/d control register 2 adcon2 00 16 a/d control register 1 adcon1 00 16 port p0 register p0 xx 16 port p0 direction register pd0 00 16 port p1 register p1 xx 16 port p1 direction register pd1 00 16 port p3 register p3 xx 16 port p3 direction register pd3 00 16 port p4 register p4 xx 16 port p4 direction register pd4 00 16 pull-up control register 0 pur0 00xx0000 2 port p1 drive capacity control register drr 00 16 register symbol after reset address pull-up control register 1 pur1 xxxxxx0x 2 flash memory control register 1 fmr1 0100xx0x 2 flash memory control register 0 fmr0 00000001 2 timer c output control register tcout 00 16 flash memory control register 4 fmr4 01000000 2 x : undefined notes : 1. the blank areas, 0100 16 to 01b2 16 and 01b8 16 to 02ff 16 are reserved and cannot be used by users. table 4.4 sfr information(4) (1)
rev.1.40 sep 30, 2004 page 14 of 26 rej09b0034-0140z r8c/11 group 5. electrical characteristics 5. electrical characteristics operating ambient temperature parameter unit supply voltage output voltage v o p d power dissipation storage temperature rated value v v condition v cc t stg t opr symbol mw v cc =av cc v av cc v -0.3 to 6.5 -65 to 150 300 -20 to 85 / -40 to 85 (d version) c topr=25 c analog supply voltage v cc =av cc -0.3 to 6.5 v i input voltage -0.3 to v cc +0.3 -0.3 to v cc +0.3 c table 5.1 absolute maximum ratings table 5.2 recommended operating conditions 2 . 75 . 5 typ. m a x . unit p a r a m e t e r v c c s u p p l y v o l t a g e s y m b o l m i n . s t a n d a r d a n a l o g s u p p l y v o l t a g e v c c 3 a v c c v v 0 0 a n a l o g s u p p l y v o l t a g e s u p p l y v o l t a g e v i h v s s a v s s 0 . 8 v c c v v v cc 0.2v cc " l " i n p u t v o l t a g e " h " i n p u t v o l t a g e v f (x in ) main clock input oscillation frequency v v i l 10 3 . 0v v c c 5 . 5 v 2 . 7 v v c c < 3 . 0 v m h z m h z note 1: referenced to v cc = av cc = 2.7 to 5.5v at topr = -20 to 85 c / -40 to 85 c unless otherwise specified. 2: the mean output current is the mean value within 100ms. 3: hold vcc=avcc. 0 i oh (sum) "h" peak all output currents c o n d i t i o n s sum of all pins' ioh (peak) -60.0 ma i o h ( p e a k ) " h " p e a k o u t p u t c u r r e n t -10.0 ma i oh (avg) " h " a v e r a g e o u t p u t c u r r e n t - 5 . 0m a i ol (sum) " l " p e a k a l l o u t p u t c u r r e n t s sum of all pins' iol (peak) 60 m a i ol (peak) "l" peak output current except p1 0 to p1 7 p1 0 to p1 7 10 m a drive capacity high drive capacity low 30 10 ma m a i o l ( a v g ) "l" average output current except p1 0 to p1 7 p1 0 to p1 7 drive capacity high drive capacity low 5 1 5 5 m a m a m a 0 0 20
rev.1.00 sep 17, 2004 page 15 of 26 rej09b0062-0100z r8c/11 group 5. electrical characteristics table 5.3 a/d conversion characteristics standard min. typ. max. resolution bit v ref =v cc 10 symbol parameter measuring condition unit lsb ? r ladder t conv ladder resistance conversion time reference voltage analog input voltage v v ia v ref 0 v ref note 1: referenced to v cc =av cc =2.7 to 5.5v at topr = -20 to 85 ? / -40 to 85 ? unless otherwise specified. 2: when f ad is 10 mhz more, divide the f ad and make a/d operation clock frequency ( ad) lower than 10 mhz. 3: when the vcc is less than 4.2v, divide the f ad and make a/d operation clock frequency ( ad) lower than f ad /2. 4: hold vcc=vref. f(xin)=?d=10 mhz, vref=vcc=5.0v v ref =v cc absolute accuracy 10 bit mode 8 bit mode f(xin)=?d=10 mhz, vref=vcc=5.0v ? lsb 10 bit mode 8 bit mode f(xin)=?d=10 mhz, vref=vcc=3.3v ? lsb f(xin)=?d=10 mhz, vref=vcc=3.3v ? lsb 10 40 k ? ad=10 mhz, vref=vcc=5.0v f(xin)= ad=10 mhz, vref=vcc=5.0v 3.3 2.8 ? ? v a/d operation clock frequency 2 without sample & hold with sample & hold 0.25 10 mhz 1.0 10 mhz v cc 4 p0 p1 p2 p3 p4 30pf figure 5.1 port p0 to p4 measurement circuit
rev.1.40 sep 30, 2004 page 16 of 26 rej09b0034-0140z r8c/11 group 5. electrical characteristics byte program time block erase time program, erase voltage read voltage 50 0.4 s parameter standard min. typ. max unit note 1: referenced to v cc1 =avcc=2.7 to 5.5v at topr = 0 to 60 c unless otherwise specified. measuring condition symbol program, erase temperature 2.7 2.7 0 400 9 5.5 5.5 60 s v v c time delay from suspend request until erase suspend td(sr-es) program/erase cycle 8 ms 100 cycle vcc=5.0v, topr=25 c vcc=5.0v, topr=25 c data-retention duration topr=55 c 20 year table 5.4 flash memory version electrical characteristics table 5.5 voltage detection circuit electrical characteristics symbol standard typ. unit measuring condition min. max. parameter vdet voltage detection level v 3.8 4.3 notes: 1. the measuring condition is vcc=avcc=2.7v to 5.5v and topr= -40 c to 85 c. 2. this shows the time until the voltage detection interrupt request is generated since the voltage passes vdet. 3. this shows the required time until the voltage detection circuit operates when setting to "1" again after setting the vc27 bit in the vcr2 register to 0 voltage detection interrupt request generating time 2 40 na voltage detection circuit self consumption current waiting time till voltage detection circuit operation starts 3 td(e-a) vc27=1, vcc=5.0v 3.3 20 600 ? ? vccmin minimum value of microcomputer operation voltage 2.7 v fmr46 erase-suspend request (interrupt request) t d(sr-es) figure 5.2 time delay from suspend request until erase suspend
rev.1.00 sep 17, 2004 page 17 of 26 rej09b0062-0100z r8c/11 group 5. electrical characteristics symbol standard typ. unit measuring condition min. max. parameter power-on reset valid voltage notes: 1. the voltage detection circuit which is embedded in a microcomputer is a factor to generate the hardware reset 2. refer to 5 .1.2 hardware reset 2 of hardware manual. 2. this condition is not applicable when using with vcc figure 5.3 reset circuit electrical characteristics v por1 v cc min v det 3 v det 3 t w(por1) t w(vpor1 vdet) sampling time 1,2 internal reset signal ( l effective) f ring-s 1 x 32 f ring-s 1 x 32 v por2 notes: 1. hold the voltage of the microcomputer operation voltage range (vccmin or above) within sampling time. 2. a sampling clock is selectable. refer to 5.4 voltage detection circuit of hardware manual for details. 3. v det shows the voltage detection level of the voltage detection circuit. refer to 5.4 voltage detection circuit of hardware manual for details. t w(por2) t w(vpor2 vdet) symbol standard typ. unit measuring condition min. max. parameter power-on reset valid voltage notes: 1. when not the sing hardware reset 2, use with vcc c c v ms vpor1 t w(vpor1- vdet) t w(por1) time to hold external power on below valid voltage time to hold external power on below valid voltage 0.1 0.5 1 t w(vpor1- vdet) t w(por1) t w(vpor1- vdet) t w(por1) t w(vpor1- vdet) t w(por1) supply voltage rising time when power-on reset is canceled supply voltage rising time when power-on reset is canceled time to hold external power on below valid voltage supply voltage rising time when power-on reset is canceled 0 c c 0 c c -20 c c -20 c c -20 c c 0 c c 0 c c 10 30 10 1 100 ms ms ms s s s table 5.6 reset circuit electrical characteristics (when using hardware reset 2) table 5.7 reset circuit electrical characteristics (when not using hardware reset 2)
rev.1.40 sep 30, 2004 page 18 of 26 rej09b0034-0140z r8c/11 group 5. electrical characteristics table 5.10 electrical characteristics (1) [vcc=5v] symbol v oh v ol "l" output voltage "h" output voltage standard typ. unit measuring condition v v v min. max. v cc - 2.0 parameter i oh = - 5ma v hysteresis "h" input current i ih "l" input current i il v ram ram retention voltage v t+- v t- 0.2 v ? at stop mode 2.0 v i =5v v i =0v r fxin feedback resistance x in m ? ? c / -40 to 85 c, f(bclk)=20mhz unless otherwise specified. v cc except x out x out i oh = - 200a drive ability high drive ability low v cc - 0.3 v cc v i oh = - 1 ma v cc - 2.0 v cc - 2.0 i oh = - 500a v v v cc v cc p1 0 to p1 7 except x out p1 0 to p1 7 x out drive capacity high drive capacity low i oh = 5 ma i oh = 200 a i ol = 15 ma i ol = 5 ma 2.0 0.45 v 2.0 2.0 v drive capacity high drive capacity low i ol = 1 ma i ol =500 a 2.0 2.0 v reset 0.2 1.0 2.2 v 5.0 - 5.0 ? v i =0v 50 1.0 f ring-s low-speed on-chip oscillator frequency 40 250 khz int 0 , int 1 , int 2 , int 3 , ki 0 , ki 1 , ki 2 , ki 3 , cntro, cntr 1 , tc in , rxd 0 , rxd 1 drive capacity low i ol = 200 a 0.45 v v symbol standard typ. unit measuring condition min. max. parameter high-speed on-chip oscillator frequency 1 / {td(hroffset)+td(hr)} when the reset is released notes: 1. the measuring condition is vcc=avcc=5.0 v and topr=25 c. high-speed on-chip oscillator period adjusted unit mhz ns vcc=5.0v, topr=25 c set "00 16 " in the hr1 register 8 61 differences when setting "01 16 " and "00 16 " in the hr register settable high-speed on-chip oscillator minimum period high-speed on-chip oscillator temperature dependence(1) td(hroffset) td(hr) vcc=5.0v, topr=25 c set "40 16 " in the hr1 register 1 ns frequency fluctuation in temperature range of -10 c to 50 c ? % % high-speed on-chip oscillator temperature dependence(2) frequency fluctuation in temperature range of -40 c to 85 c ?0 610 table 5.8 high-speed on-chip oscillator circuit electrical characteristics symbol standard typ. unit measuring condition min. max. parameter 2 note 1: the measuring condition is vcc=avcc=2.7 to 5.5 v and topr=25 c. 2: this shows the wait time until the internal power supply generating circuit is stabilized during power-on. 3: this shows the time until bclk starts from the interrupt acknowledgement to cancel stop mode. 150 td(r-s) stop release time 3 ms td(p-r) time for internal power supply stabilization during powering-on 2 ? table 5.9 power circuit timing characteristics
rev.1.00 sep 17, 2004 page 19 of 26 rej09b0062-0100z r8c/11 group 5. electrical characteristics symbol standard typ. unit measuring condition min. max. parameter no division ma in single-chip mode, the output pins are open and other pins are v ss 9 15 x in =20 mhz (square wave) ma high-speed mode i cc power supply current (v cc =3.3 to 5.5v) 470 notes 1: the power supply current measuring is executed using the measuring program on frash memory. 2: timer y is operated with timer mode. ma medium-speed mode high-speed on-chip oscillator mode low-speed on-chip oscillator mode high-speed on-chip oscillator off low-speed on-chip oscillator on=125 khz x in =16 mhz (square wave) high-speed on-chip oscillator off low-speed on-chip oscillator on=125 khz no division 8 x in =20 mhz (square wave) high-speed on-chip oscillator off low-speed on-chip oscillator on=125 khz division by 8 4 x in =16 mhz (square wave) high-speed on-chip oscillator off low-speed on-chip oscillator on=125 khz division by 8 3 ma main clock off high-speed on-chip oscillator on=8 mhz low-speed on-chip oscillator on=125 khz no division 4 8 ma main clock off low-speed on-chip oscillator on=125 khz division by 8 ma 1.5 main clock off high-speed on-chip oscillator off low-speed on-chip oscillator on=125 khz high-speed on-chip oscillator on=8 mhz ma x in =10 mhz (square wave) high-speed on-chip oscillator off low-speed on-chip oscillator on=125 khz no division 5 x in =10 mhz (square wave) high-speed on-chip oscillator off low-speed on-chip oscillator on=125 khz division by 8 2 ma 14 900 wait mode a division by 8 main clock off high-speed on-chip oscillator off low-speed on-chip oscillator on=125 khz when a wait instruction is executed 2 peripheral clock operation 40 a wait mode main clock off high-speed on-chip oscillator off low-speed on-chip oscillator on=125 khz when a wait instruction is executed 2 peripheral clock off 38 76 80 a stop mode main clock off high-speed on-chip oscillator off low-speed on-chip oscillator off cm10="1" peripheral clock off 0.8 3.0 vc27="0" vc27= 0 vc27= 0 ? table 5.11 electrical characteristics (2) [vcc=5v]
rev.1.40 sep 30, 2004 page 20 of 26 rej09b0034-0140z r8c/11 group 5. electrical characteristics timing requirements (unless otherwise noted: v cc = 5v, v ss = 0v at ta = 25 ?) [v cc =5v] table 5.12 x in input ________ table 5.13 cntr0 input, cntr1 input, int2 input ________ table 5.14 tcin input, int3 input table 5.15 serial interface ________ table 5.16 external interrupt int0 input symbol t c (x in ) t wh (x in ) t wl (x in ) parameter x in input cycle time x in input high pulse width x in input low pulse width min. 50 25 25 max. unit ns ns ns standard symbol t c ( cntr0 ) t wh ( cntr0 ) t wl ( cntr0 ) parameter cntr0 input cycle time cntr0 input high pulse width cntr0 input low pulse width min. 100 40 40 max. unit ns ns ns standard symbol t c ( tcin ) t wh ( tcin ) t wl ( tcin ) parameter tcin input cycle time tcin input high pulse width tcin input low pulse width min. 400 (1) 200 (2) 200 (2) max. unit ns ns ns standard notes 1 :when using the timer c input capture mode, adjust the cycle time above ( 1/ timer c count source frequency x 3). 2 : when using the timer c input capture mode, adjust the pulse width above ( 1/ timer c count source frequency x 1.5). notes ________ ________ 1 : when selecting the digital filter by the int0 input filter select bit, use the int0 input high pulse width to the greater value,either ( 1/ digital filter clock frequency x 3) or the minimum value of standard. ________ ________ 2 : when selecting the digital filter by the int0 input filter select bit, use the int0 input low pusle width to the greater value,either ( 1/ digital filter clock frequency x 3) or the minimum value of standard. symbol t c ( ck ) t w ( ckh ) t w ( ckl ) t d ( c-q ) t h ( c-q ) t su ( d-c ) t h ( c-d ) parameter clki input cycle time clki input high pulse width clki input low pulse width txdi output delay time txdi hold time rxdi input setup time rxdi input hold time min. 200 100 100 0 35 90 max. unit ns ns ns ns ns ns ns standard 80 symbol t w ( inh ) t w ( inl ) parameter ________ int0 input high pulse width ________ int0 input low pulse width min. 250 (1) 250 (2) max. unit ns ns standard
rev.1.00 sep 17, 2004 page 21 of 26 rej09b0062-0100z r8c/11 group 5. electrical characteristics figure 5.4 vcc=5v timing diagram clk i txd i rxd i int i t w(ckh) t c(ck) t w(ckl) t h(c-q) t h(c-d) t su(d-c) t d(c-q) t w(inl) t w(inh) x in input t wh(xin) t c(xin) t wl(xin) tcin input t wh(tcin) t c(tcin) t wl(tcin) cntr0 input t wh(cntr0) t c(cntr0) t wl(cntr0) v cc = 5v
rev.1.40 sep 30, 2004 page 22 of 26 rej09b0034-0140z r8c/11 group 5. electrical characteristics symbol v oh v ol "l" output voltage "h" output voltage standard typ. unit measuring condition v v v min. max. v cc - 0.5 parameter i oh = - 1ma v hysteresis "h" input current i ih "l" input current i il v ram ram retention voltage v t+- v t- 0.2 v a at stop mode 2.0 v i =3v r fxin feedback resistance x in m ? ? c / -40 to 85 c, f(bclk)=10mhz unless otherwise specified. v cc except x out x out drive capacity high drive capacity low i oh = - 0.1 ma v cc - 0.5 v cc - 0.5 i oh = - 50 a v v v cc v cc p1 0 to p1 7 except x out p1 0 to p1 7 x out drive capacity high drive capacity low i oh = 1 ma i ol = 2 ma i ol = 1 ma 0.5 v 0.5 0.5 v drive capacity high drive capacity low i ol = 0.1 ma i ol =50 a 0.5 0.5 v int 0 , int 1 , int 2 , int 3 , ki 0 , ki 1 , ki 2 , ki 3 , cntro, cntr 1 , tc in , rxd 0 , rxd 1 reset 0.2 0.8 1.8 v 4.0 - 4.0 ? v i =0v 160 3.0 f ring-s low-speed on-chip oscillator frequency 40 250 khz v i =0v 500 table 5.17 electrical characteristics (3) [vcc=3v]
rev.1.00 sep 17, 2004 page 23 of 26 rej09b0062-0100z r8c/11 group 5. electrical characteristics table 5.18 electrical characteristics (4) [vcc=3v] symbol standard typ. unit measuring condition min. max. parameter no division ma in single-chip mode, the output pins are open and other pins are v ss 8 13 x in =20 mhz (square wave) ma high-speed mode i cc power supply current (v cc =2.7 to 3.3v) 420 note 1: the power supply current measuring is executed using the measuring program on frash memory. 2: timer y is operated with timer mode. wait mode ? ? ma medium-speed mode high-speed on-chip oscillator mode low-speed on-chip oscillator mode high-speed on-chip oscillator off low-speed on-chip oscillator on=125 khz x in =16 mhz (square wave) high-speed on-chip oscillator off low-speed on-chip oscillator on=125 khz no division 7 x in =20 mhz (square wave) high-speed on-chip oscillator off low-speed on-chip oscillator on=125 khz division by 8 3 x in =16 mhz (square wave) high-speed on-chip oscillator off low-speed on-chip oscillator on=125 khz division by 8 2.5 ma main clock off high-speed on-chip oscillator on=8 mhz low-speed on-chip oscillator on=125 khz no division 3.5 7.5 ma main clock off low-speed on-chip oscillator on=125 khz division by 8 ma 1.5 main clock off high-speed on-chip oscillator off low-speed on-chip oscillator on=125 khz division by 8 main clock off high-speed on-chip oscillator off low-speed on-chip oscillator on=125 khz when a wait instruction is executed 2 peripheral clock operation 37 high-speed on-chip oscillator on=8 mhz ma x in =10 mhz (square wave) high-speed on-chip oscillator off low-speed on-chip oscillator on=125 khz no division 5 x in =10 mhz (square wave) high-speed on-chip oscillator off low-speed on-chip oscillator on=125 khz division by 8 1.6 ma 12 800 ? wait mode main clock off high-speed on-chip oscillator off low-speed on-chip oscillator on=125 khz when a wait instruction is executed 2 peripheral clock off 35 70 74 stop mode main clock off high-speed on-chip oscillator off low-speed on-chip oscillator off cm10="1" peripheral clock off 0.7 3.0 vc27="0" vc27= 0 vc27= 0 ?
rev.1.40 sep 30, 2004 page 24 of 26 rej09b0034-0140z r8c/11 group 5. electrical characteristics timing requirements (unless otherwise noted: v cc = 3v, v ss = 0v at ta = 25 ?) [v cc =3v] table 5.19 x in input ________ table 5.20 cntr0 input, cntr1 input, int2 input ________ table 5.21 tcin input, int3 input table 5.22 serial interface ________ table 5.23 external interrupt int0 input symbol t c (x in ) t wh (x in ) t wl (x in ) parameter x in input cycle time x in input high pulse width x in input low pulse width min. 100 40 40 max. unit ns ns ns standard symbol t c ( cntr0 ) t wh ( cntr0 ) t wl ( cntr0 ) parameter cntr0 input cycle time cntr0 input high pulse width cntr0 input low pulse width min. 300 120 120 max. unit ns ns ns standard symbol t c ( tcin ) t wh ( tcin ) t wl ( tcin ) parameter tcin input cycle time tcin input high pulse width tcin input low pulse width min. 1200 (1) 600 (2) 600 (2) max. unit ns ns ns standard notes 1 :when using the timer c input capture mode, adjust the cycle time above ( 1/ timer c count source frequency x 3). 2 : when using the timer c input capture mode, adjust the pulse width above ( 1/ timer c count source frequency x 1.5). notes ________ ________ 1 : when selecting the digital filter by the int0 input filter select bit, use the int0 input high pulse width to the greater value,either ( 1/ digital filter clock frequency x 3) or the minimum value of standard. ________ ________ 2 : when selecting the digital filter by the int0 input filter select bit, use the int0 input low pusle width to the greater value,either ( 1/ digital filter clock frequency x 3) or the minimum value of standard. symbol t c ( ck ) t w ( ckh ) t w ( ckl ) t d ( c-q ) t h ( c-q ) t su ( d-c ) t h ( c-d ) parameter clki input cycle time clki input high pulse width clki input low pulse width txdi output delay time txdi hold time rxdi input setup time rxdi input hold time min. 300 150 150 0 55 90 max. unit ns ns ns ns ns ns ns standard 160 symbol t w ( inh ) t w ( inl ) parameter ________ int0 input high pulse width ________ int0 input low pulse width min. 380 (1) 380 (2) max. unit ns ns standard
rev.1.00 sep 17, 2004 page 25 of 26 rej09b0062-0100z r8c/11 group 5. electrical characteristics figure 5.5 vcc=3v timing diagram clk i txd i rxd i int i t w(ckh) t c(ck) t w(ckl) t h(c-q) t h(c-d) t su(d-c) t d(c-q) t w(inl) t w(inh) x in input t wh(xin) t c(xin) t wl(xin) tcin input t wh(tcin) t c(tcin) t wl(tcin) cntr0 input t wh(cntr0) t c(cntr0) t wl(cntr0) v cc = 3v
rev.1.40 sep 30, 2004 page 26 of 26 rej03b0034-0140z r8c/11 group package dimensions package dimensions lqfp32-p-0707-0.80 weight(g) ? jedec code eiaj package code lead material cu alloy 32p6u-a plastic 32pin 7 ? 7mm body lqfp ? 0.1 ? ?? 0.2 ? ? ?? ? ? ? ? ? symbol min nom max a a 2 b c d e h e l l 1 y b 2 dimension in millimeters h d a 1 ? ? i 2 1.0 ? ? m d ? ? m e 10? 0? 0.1 1.0 0.7 0.2 0.5 0.3 0.8 6.9 7.0 7.1 6.9 7.0 7.1 8.8 9.0 9.2 8.8 9.0 9.2 0.175 0.125 0.105 0.45 0.37 0.32 1.4 0 1.7 e lp 0.45 ? ? 0.6 0.5 7.4 7.4 0.25 ? 0.75 ? x a3 recommended mount pad detail f a e h e h d d 1 8 24 17 25 32 16 9 m d b 2 m e e f e y b x m a 1 a 2 l l 1 lp a3 c i 2
revision history r8c/11 group datasheet rev. date description page summary a-1 1.00 jun. 19, 2003 first edition issued 1.10 sep. 08, 2003 table 1.1: shortest instruction execution time and f(x in ) changed ____________ figure 1.3: pin name changed from tx out to cntr 0 ____________ table 1.3: pin name changed from tx out to cntr 0 the value of hr1 register after reset changed the value of tc register after reset changed chapter ?. electrical characteristics?added 2 5 6 10 12 14 1.20 oct. 31, 2003 table 1.1: power consumption values added table 1.3: resistor value for cnvss and mode deleted register name of address 0050 16 modified from cmp2ic to cmp1ic, register name of address 005c 16 modified from cmp1ic to cmp0ic table 5.2: note 3 and note 4 deleted t samp in table 5.3 deleted figure 5.1 added table 5.10: vcc changed from ?.2 to 5.5v?to ?.3v to 5.5v? low-power ring oscil- lator changed from ?n 100khz?to ?25khz? x in =5mhz deleted and x in =10mhz added in high-speed mode and medium-speed mode, vc27=??added in stop mode measuring condition, data added and modified table 11 to table 15 added figure 5.2 added table 5.16: note 1, f (bclk) =5 mhz changed to 10 mhz table 5.17: low-power ring oscillator changed from ?n 100khz?to ?25khz? x in =5mhz deleted and x in =10mhz added in high-speed mode and medium-speed mode, vc27=??added in stop mode measuring condition, data added and modi- fied table 5.18 to table 5.22 added figure 5.3 added 2 6 11 14 15 17 19 20 21 22 23 24 25 1.30 dec 05, 2003 4 table 1.2 : ** deleted 15 table 5.4 revised 1.40 sep 30, 2004 all pages words standardized (on-chip oscillator, serial interface, a/d) 2 table 1.1 revised 5 figure 1.3, notes 3 added 6 table 1.3 revised 9 figure 3.1, notes added 10-13 one body sentence in chapter 4 added ; title of table 4.1 to 4.4 added 12 table 4.3 revised ; table 4.4 revised 14 table 5.2 revised 15 table 5.3 revised 16 table 5.4 revised ; table 16.5 revised 17 table 5.6, 5.7 adn 5.8 revised ; figure 5.3 revised 18 table 5.9 revised ; table 5.10 revised
revision history r8c/11 group datasheet rev. date description page summary a-2 1.40 sep 30, 2004 20 table 5.12 revised ; table 5.16 revised 22 table 16.17 revised 24 table 16.19 revised
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